A 3D electronic module, an example of which is shown in FIG. 1, comprises a stack 100 of electronic slices 50 that are interconnected in three dimensions by using notably the faces of the stack to produce the connections between the slices. One slice 50 usually comprises one or more active and/or passive components 11 that have electrical connection elements 2, the components being coated in an electrically insulating resin 6. The connection elements 2 of the components are connected to connection pins 2′ supported by an electrically insulating substrate 4. One or more electrically conductive tracks 3 supported by the insulating substrate 4 connect these components together or connect them to elements for electrically connecting the slices together. A 3D electronic module comprises at least one active component in one of the slices.
These slices 50 have preferably been obtained by collective fabrication from reconstructed wafers also called KGRWs which stands for Known Good Reconstructed Wafers, themselves made during the following steps:                A) Position and fasten to a substrate bare (=not encapsulated) active and/or passive silicon components 11 furnished with their connection pins 2, these components preferably having already been validated after a test; the connection pins are in contact with the substrate. This substrate is typically an adhesive sheet of the sticky skin type.        B) Place on the components and substrate assembly a polymer layer such as the epoxy resin 6.        C) Remove the substrate (the sticky skin),        D) Redistribute the pins to connect all of the components 11 of one and the same pattern and/or make connections to the periphery of the pattern for the purpose of a subsequent 3D interconnection. For this purpose, a layer of an insulating material 4 of the etchable polymer type on which metal conductive tracks 3 are formed providing the connection of the component 11 to other components and/or to the periphery is placed. An insulating layer 4 is optionally placed on the conductive tracks 3. In certain cases of complex connections, several insulator+metal+optional insulator (=level) layers can be placed on one another. This has produced a redistribution layer 30 called RDL layer with one or more levels. In the figure, the RDL layer of each slice 50 has a single level.                    This has produced a “KGRW” reconstructed wafer which therefore comprises only previously tested and validated slices.                        E) When several KGRW wafers have been fabricated they are then stacked.        F) A pin redistribution layer 30, called RDL for ReDistribution Layer, is formed on one of the faces of the stack, thus forming the “first” layer of the stack. This RDL layer typically comprises 1 to 4 levels (or sublayers) and is formed on the stack of wafers before the cutting step, that is to say during the collective fabrication method. In the figure it has two levels.        
The stack of wafers is cut to obtain stacks 100 of slices.
Conductors 33 situated on the lateral faces of the stack of slices, that is to say on the edges of the slices and optionally on one of the faces, and called lateral conductors, are formed to electrically connect the components of one slice to the other.
An example of such a method is described in patent FR 2 857 157.
However it is often necessary to have, for one slice 50 and/or for the first layer of the stack 100 of slices, a redistribution layer (RDL) of more than 4 levels: 6 to 10 connection levels are often necessary. But the yield of the RDL layers falls rapidly with the increase in the number of levels. For one slice, it falls typically from an yield of 96% with an RDL with one level to 80% for an RDL with four levels; RDLs with 6 levels or more are therefore not produced.
As a consequence, there now remains a need for a method for collective fabrication of 3D electronic modules that simultaneously satisfies all the aforementioned requirements in terms of number of redistribution layers and of yield (number validated/number fabricated).